Semiconductor devices of recent years have become large-scaled and high speed, and a number of functions are incorporated and systematized. In these semiconductor devices, transistors are miniaturized for a large scale and high speed, whereby operation speed is improved. Further, for systematization, not only various functional blocks including a CPU but also various memory devices are mixed and mounted. In memory devices mixed and mounted on these system LSIs, for example, Static Random Access Memory (SRAM, hereinafter, referred to as a SRAM for short) mixed and mounted for use of a cache memory and the like, transistors constructing an SRAM are to be miniaturized, whereby a large-scaled and/or high-speed operation is promoted.
A general-purpose SRAM will be described with reference to drawings. A memory cell of the SRAM (hereinafter, referred to as a SRAM cell for short) constructed from 6 transistors is shown in FIG. 1. In the case where a word line WL is a low potential, two Complementary Metal Oxide Semiconductor (CMOS) inverters form a loop, whereby it is possible to hold data stably. Namely, one CMOS inverter outputs inverted data of data stored in a storage node V1 to a storage node V2 when the storage node V1 is used as an input, while the other CMOS inverter outputs inverted data of data stored in the storage node V2 to the storage node V1 when the storage node V2 is used as an input.
In the case where the word line WL is accessed to be a high potential, NMOS access transistors N3 and N4 conduct. At this time, the data stored in the storage nodes V1 and V2 are outputted to bit lines BL and /BL that are charged to a high potential, thereby becoming a reading operation of the memory. Moreover, one bit line is discharged to a low potential in accordance with writing data, and data are inputted from the bit lines BL and /BL to the storage nodes V1 and V2, thereby becoming a writing operation of the memory.
There is a CMOS latch circuit as representative one among memory elements constructed from a CMOS gate. In the CMOS latch circuit, a CMOS switch is inserted into a CMOS inverter loop, and the CMOS inverter loop is cut off at a writing operation, whereby a writing input terminal becomes a high impedance state to achieve a stable writing operation.
On the other hand, in a SRAM cell, a CMOS switch for cutting off the inverter loop is omitted because of a small area thereof. Alternatively, by providing a complementary input to the two storage nodes V1 and V2 of the CMOS inverter loop through NMOS access transistors N3 and N4, a writing operation can be carried out without a writing input becoming a high impedance state. In this case, a condition to carry out a writing operation stably is that drive capability of the NMOS access transistors (N3 and N4) is greater than drive capability of the PMOS load transistors (P1 and P2).
However, in SRAMs after the 90 nm generation, a problem that variation in width of transistor drive capability is increased becomes obvious because the transistor is miniaturized for a large scale and a high-speed operation. In other words, possibility that the drive capability of the NMOS access transistor becomes smaller than the drive capability of the PMOS load transistor is heightened. As a result, a problem occurs that data cannot be written in a SRAM cell in which a writing operation condition is not met. This problem may also occur in the case where power source voltage of the overall SRAM is lowered for low power.
In Non-Patent Document 1 (K. Zhang et. al., “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” ISSCC Dig. Tech. Papers, pp. 474-475, February 2005), measures to ease a writing operation condition are taken with respect to this problem. As well as one shown in FIG. 11 (will be described later), a power source connected to a source terminal of a PMOS load transistor is somewhat stepped down only at a writing operation, whereby gate-source voltage Vgs of the PMOS load transistor is decreased and the drive capability of the load transistor is decreased. Thus, the drive capability of the NMOS access transistors (N3 and N4) becomes greater than the drive capability of the PMOS load transistors (P1 and P2), and a stable writing operation is achieved.
Further, in Non-Patent Document 2 (M. Yamaoka et. al., “Low-Power Embedded SRAM Modules with Expanded Margins for Writing,” ISSCC Dig. Tech. Papers, pp. 480-481, February 2005), as shown in FIG. 24, in order to reduce a leakage current of an NMOS cell transistor, a power source Vssm connected to a source terminal of each of NMOS drive transistors (N1 and N2) is cut off from a substrate potential GND while it is not accessed. The power source Vssm is charged due to the leakage current of the SRAM cell, and the power source Vssm converges at a potential somewhat higher than the substrate potential GND. This power source Vssm is applied to a gate terminal of the PMOS load transistor through the NMOS drive transistor that is turned on. Thus, since the gate-source Vgs is decreased and the drive capability of the PMOS load transistor is decreased, an effect that the writing operation condition similar to that in Non-Patent Document 1 is eased is provided.
By carrying out the power source control as described above, a stable writing operation can be carried out even in the SRAMs after the 90 nm generation. However, in the case where the power source control is carried out more than necessary, the drive capability of the PMOS load transistor is deteriorated largely. There is a problem that writing time for charging one of the storage nodes in the SRAM cell from a low potential to a high potential gets longer significantly.